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VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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DOCUMENT REVISION HISTORY 1: DOCUMENT DATE DESCRIPTION REVISION FROM TO A 2002.01.09 First Release (Based on the test specification VL-TS-MGLS12864T-65, REV. A, 2001.03.14) B 2004.09.17 Items 1 to 6 were updated. Based on a.) VL-TS-MGLS12864T-XX REV.R. 2004.06.05. b.) VL-QUA-012A REV.R. 2004.03.20 According to VL-QUA-012A, LCD size is small because Unit Per Laminate = 12 which is more than 6pcs/Laminate. 1.) (Page3) Contents were updated. 2.) (Page4, Point 1) In general description "FPC connection" was added. 3.) (Page5,Figure1) Module Specification was updated. 4.) (Page6,Point 3.1) "Electrical Maximum Ratings (Ta = 25 C)" was updated to "Electrical Maximum Ratings - for IC Only" 5.) (Page8, Point 4.2) The value of IDD&I0 were updated. 6.) (Page11, Point 5&6) "LCD commend condition" and "Remark" were added.
CHANGED BY PHILIP CHENG
CHECKED BY TOM LEE
ZHANG YAN FANG
FRANK WANG
VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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CONTENTS
Page No. 1. 2. 3. 3.1 3.2 4. 4.1 4.2 4.3 4.4 5. 6. GENERAL DESCRIPTION MECHANICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ELECTRICAL MAXIMUM RATINGS - FOR IC ONLY ENVIRONMENTAL CONDITION ELECTRICAL SPECIFICATIONS INTERFACE SIGNALS TYPICAL ELECTRICAL CHARACTERISTICS TIMING SPECIFICATIONS TIMING DIAGRAM OF VDD AGAINST V0 LCD COSMETIC CONDITIONS REMARK 4 4 6 6 6 7 7 8 8 10 11 11
VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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VARITRONIX LIMITED
Specification of LCD Module Type Item No.: MGLS12864T-65
1. General Description * * * * * * * * * 128 x 64 dot matrix FSTN LV2 positive black & white reflective dot matrix LCD graphic module. Viewing direction: 6 o'clock. Driving scheme: 1/64 multiplexed drive, 1/9.3 bias. `Toshiba' T6963C flat pack or equivalent dot matrix LCD controller. `Toshiba' T6A39 flat pack or equivalent dot matrix liquid crystal graphic display column drivers. `Toshiba' T6A40 flat pack or equivalent dot matrix liquid crystal graphic display row driver. 8K byte display SRAM. Enhancement film - TDF `3M'. FPC Connection.
2.
Mechanical Specifications The mechanical detail is shown in Fig. 1 and summarized in Table 1 below. Table 1 Specifications 78.0(W) x 70.0(H) x 10.5 MAX.(D) 128(Horizontal) x 64(Vertical) 62.0(W) x 44.0(H) 56.27(W) x 38.35(H) 0.39(W) x 0.55(H) 0.05(W) x 0.05(H) 0.44(W) x 0.60(H) TBD Unit mm dots mm mm mm mm mm grams
Parameter Outline dimensions Display format Viewing area Active area Dot size Dot spacing Dot pitch Weight:
VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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Figure 1: Specification Drawing
VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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3. 3.1
Absolute Maximum Ratings Electrical Maximum Ratings - for IC Only Table 2 Parameter Symbol Min. Max. Unit Supply voltage (Logic & LCD) VDD - VSS -0.3 +7.0 V Supply voltage (LCD drive) VLCD -0.3 +30.0 V (Built-in) =VDD - V0 Input voltage Vin -0.3 VDD+0.3 V Note: The modules may be destroyed if they are used beyond the absolute maximum ratings. All voltage values are referenced to VSS = 0V.
3.2
Environmental Condition Table 3 Operating Storage Temperature Temperature (Topr) (Tstg) Min. Max. Min. Max. 0C +50C -10C +60C 95% max. RH for Ta 40C < 95% RH for Ta > 40C Frequency: 10 55 Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction. Pulse duration : 11 ms Peak acceleration: 981 m/s2 = 100g Number of shocks : 3 shocks in 3 mutually perpendicular axes.
Item Ambient Temperature Humidity Vibration (IEC 68-2-6) cells must be mounted on a suitable connector Shock (IEC 68-2-27) Half-sine pulse shape
Remark Dry no condensation 3 directions 3 directions
VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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4. 4.1
Electrical Specifications Interface signals Table 4
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 -
Symbol FG VSS VDD V0 /WR /RD /CE C/D /RST DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 FS A K
Description Frame ground (see note 1). Ground (0V). Power supply for logic (+5V). Power supply for LCD drive Data Write. Write data into T6963C when /WR="Low". Data Read. Read data from T6963C when /RD="Low". Chip enable for T6963C. /CE must be "Low" when CPU communicates with T6963C. /WR = "Low" .....C/D="High": Command Write C/D="Low": Data Write. /RD = "Low" ..... C/D="High": Status Read C/D="Low": Data Read. "High": Normal (T6963C has internal pull-up resistor). "Low": Initialize T6963C. Text and graphic have addresses and text and graphic area settings are retained. Data input/output (LSB). Data input/output. Data input/output. Data input/output. Data input/output. Data input/output. Data input/output. Data input/output (MSB). Font select. "High" for 6 x 8 font & "Low" for 8 x 8 font. Anode of backlight Cathode of backlight
Note 1: This pin is electrically connected to the metal bezel (frame). User can choose to connect this pin to VSS or leave it open.
VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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4.2
Typical Electrical Characteristics At Ta = 25 C, VDD = +5V5%, VSS=0V. Table 5
Parameter Supply voltage (Logic & LCD) Supply voltage (LCD) Input signal voltage
Symbol VDD -VSS VLCD =VDD -V0 VIH VIL IDD
Conditions VDD = 5V, Note 1
Min. 4.75 9.5
Typ. 5.00 10.0
Max. 5.25 10.5
Unit V V
"H" level VDD-2.2 VDD V "L" level 0 0.8 V Supply current Character mode, VDD 7.0 10.0 mA (Logic & LCD) = 5V, Note 1 Checker board mode, 7.6 11.4 mA VDD = 5V, Note 1 Supply current (LCD) I0 Character mode, 2.8 4.2 mA VDD = 5V, Note 1 Checker board mode, 2.8 4.2 mA VDD = 5V, Note 1 Note (1): There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. 4.3 Timing Specifications At Ta = 0 C To +50 C, VDD = +5V5%, VSS = 0V. Refer to Fig. 2, the bus timing diagram. Table 6 Parameter C/D Set-up time C/D Hold Time /CE,/RD,/WR Pulse Width Data Set-up Time Data Hold Time Access Time Output Hold Time Symbol tCDS tCDH tCE, tRD, tWR tDS tDH tACC tOH Min. 100 10 80 80 40 10 Max. 150 50 Unit ns ns ns ns ns ns ns
VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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C/D
t CDS
t CDH
CE t CE.t RD.t WR RD. WR t DS
DB0~DB7
(WRITE) (WRITE)
D0~D7
t DH
DB0~DB7 D0~D7
(READ) (READ)
t ACC
t OH
Figure 2: Bus Timing Diagram
VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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4.4
Timing Diagram of VDD against V0.
Power on sequence shall meet the requirement of Figure 3, the timing diagram of VDD against V0.
VDD
95%
LOGIC SUPPLY VOLTAGE 0V 50ms(typical)
OV LCD SUPPLY VOLTAGE
V0
Figure 3: Timing diagram of VDD against V0.
VL-FS-MGLS12864T-65 REV. B (MGLS12864T-FSTN-0.7MM-TDF FILM) SEP/2004
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5
LCD Cosmetic Conditions a.) Reference document follow VL-QUA-012A. b.) LCD size of the product is small. Remark: a.) Identification labels will be stuck on the module without obstructing the viewing area of display, b.) Varitronix does not responsible for any polarizer defect after the protective film has been removed from the display.
6.
"Varitronix Limited reserves the right to change this specification." FAX: (852) 2343-9555. URL: http://www.varitronix.com - END -

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